(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor element structure in which a fine pattern can be formed with high controllability.
(2) Description of the Related Art
Active research on making semiconductor elements finer and more dense is in progress and, nowadays, there have been developed test devices such as a memory device designed with a size standard of 0.15-0.25 .mu.m or an ultra high integrated semiconductor device such as a logic device. With advancement of high integration in a semiconductor devices, the size of the semiconductor elements is becoming increasingly finer. Thus, it is becoming more important to reduce the width of gate electrodes, the width of diffusion layers, the size of contact holes interconnecting wiring layers, the film thickness of materials constituting semiconductor elements, etc.
Any variations in pattern sizes of finely formed elements of semiconductor elements, especially any variations in gate electrode widths, produce the largest influence on the characteristics of an insulated-gate field effect transistor (hereinafter called "MOS transistor"). Also, in the contact hole interconnecting the wiring layers, a reduction in the size thereof or an increase in the aspect ratio thereof makes it difficult to ensure the reliability of the semiconductor element. For this reason, it is essential in the manufacture of the semiconductor device to reduce the variations in the sizes concerned.
Thus, as the semiconductor element becomes finer, it becomes more important to have a higher degree of control of patterns constituting semiconductor elements.
A method for fabricating the above prior art semiconductor element is explained with reference to FIGS. 1A-1F. They are sectional views showing a structure under fabrication for use in explaining sequential steps for forming a gate electrode or a gate electrode interconnect.
As shown in FIG. 1A, a pad oxide film 102 is formed on a silicon substrate 101 by a thermal oxidation process, and a silicon nitride film is formed on the pad oxide film 102 by an LPCVD (Low Pressure Chemical Vapor Deposition) process. The silicon nitride film at a portion corresponding to an element isolation region is removed by photolithography and dry-etching processes whereby a mask nitride film 103 is formed. Thereafter, as shown in FIG. 1B, by a thermal oxidation process, the silicon substrate 101 at a portion where the element isolation region is formed is selectively oxidized using the mask nitride film 103 as a mask whereby a field oxide film 104 is formed.
Next, a thin silicon oxide film formed on the mask nitride film 103 is removed by wet-etching with a buffered hydrofluoric acid solution. Then, the mask nitride film 103 is removed by etching using a phosphoric acid solution at a high temperature. Then, the pad oxide film 102 is removed by etching with a buffered hydrofluoric acid solution. In this way, as shown in FIG. 1C, the silicon substrate 101 is selectively exposed.
In the series of wet-etchings explained above, the field oxide film 104 is also etched and its thickness is reduced. Here, the time that is required for each of the steps of etching of the silicon oxide film on the surface of the mask nitride film 103, etching of the mask nitride film 103 and etching of the pad oxide film 102, is taken into account for setting the time for the complete removal of each insulating film. For this reason, the control of the thickness of the field oxide film 104 after the thickness has been reduced as explained above is not sufficient.
Next, as shown in FIG. 1D, a gate oxide film 105 is formed on the exposed surface of the silicon substrate 101 by a thermal oxidation process. Then, a polycide film 106 is deposited by LPCVD and sputtering processes. This polycide film 106 is one in which a phosphorus impurity has been introduced by a diffusion process or an ion implantation process. Next, a photoresist film 107 is applied on the entire resulting surface. The photoresist used is a known positive type photoresist.
As to the photoresist film applied, as shown in FIG. 1D, if the thickness of the photoresist 107 over the region of the field oxide film 104 is made d.sub.1 ' and the thickness of the photoresist 107 over the region of the gate oxide film 105 is made d.sub.0 ', then d.sub.1 ' is smaller than d.sub.0 ' by the magnitude of the underlying layer step formed by the difference between the upper surface of the field oxide film 104 and the upper surface of the gate oxide film 105. This value of the difference is shown by S.sub.0 in FIG. 1D.
Next, the transfer of the mask projection pattern 108 onto the photoresist film 107 is carried out using a step-and-repeat projection exposure system (hereinafter referred to as a "stepper"). Here, the size of the mask projection pattern 108 is made L.sub.0. Also, as the photosensitive illuminating light 109 of the stepper, i-ray having a wavelength of 365 nm is used. In this way, the resist patterns 110 and 111 as shown in FIG. 1E are formed. Here, the size of the resist pattern 110 formed on the region of the gate oxide film 105 is made L.sub.1 ', and the size of the resist pattern 111 formed on the region of the field oxide film 104 is made L.sub.2 '.
Thereafter, the polycide film 106 described above is etched by dry-etching using the resist patterns 110 and 111 as etching masks. In this way, as shown in FIG. 1F, a gate electrode 112 is formed on an active element region, that is, gate oxide film 105, and a gate electrode interconnect 113 on an element isolation region, that is, a field oxide film 104.
In the prior art techniques explained above, the underlying layer step S.sub.0 between the surface of the field oxide film 104 and the surface of the gate oxide film 105 is determined independently of the photolithography process step. Generally, a parasitic MOS transistor is formed at the element isolation region, but the thickness of the field oxide film 104 is set such that the threshold voltage of this parasitic MOS transistor is sufficiently high. The stepped portion which develops between the surfaces of the field oxide film 104 and the gate oxide film 105 remains uncontrolled.
Thus, for the reason that, where the thickness of the photoresist film on the active element region is d.sub.0 ', the thickness of the photoresist on the element isolation region becomes d.sub.1 '(=d.sub.0 '-S.sub.0), there arise problems that may be grouped into the two kinds explained below.
The first kind of problem is as follows. Where the transfer is made of the mask projection patterns 108 both having the same size L.sub.0 between the active element region and the element isolation region, the exposure condition is set such that the size of the resist pattern 110 on the active element region after the exposure and development becomes L.sub.0. In such a case, the thickness of the photoresist film on the element isolation region becomes thinner than that on the active element region as explained above and, as a result, the size L.sub.2 ' of the resist pattern 111 formed on the element isolation region becomes smaller than the size L.sub.1 of the resist pattern 110 on the active element region. Consequently, there arises a large deviation in the sizes, that is, L.sub.1 '-L.sub.2 '. For example, as explained above, in the case where the exposure is made using i-ray on the polycide film, if the reduced mask projection patterns 108 are set such that their sizes are of the same pattern of 0.5 .mu.m and L.sub.1 becomes 0.5 .mu.m, the size L.sub.2 ' becomes 0.4 .mu.m which is smaller by about 20%. As a result, the interconnect resistance increases, leading to a disadvantageous state in the designing of the semiconductor device. The deviation in the sizes becomes more distinct when the designing sizes are further reduced and reach a deep submicron region such as about 0.2 .mu.m.
The second kind of the problem is as follows. Where The exposure condition is set such that, by controlling the resist pattern 111 on the element isolation region, the size L.sub.2 ' thereof becomes L.sub.0, the size L.sub.1 ' of the resist pattern 110 becomes larger than L.sub.0 ', but this value is largely influenced by the underlying layer step, that is, the final value of S.sub.0. This means that the variation in the sizes of the resist patterns 110 on the active element region becomes large. This variation results in a variation in sizes of the gate electrode 112, and causes the characteristics of transistors to be varied thereby lowering the reliability of the MOS transistors.